The present invention relates to semiconductor devices, masks, and processes for forming or designing them and, more particularly, to process-assist features located at or near via locations.
In the semiconductor manufacture process, the various process steps and their sequence can yield non-planar topographical features of the semiconductor device. The topographical features are necessary in order to provide desired function in the device. The topographical variation caused by the features, however, can present certain problems in the semiconductor manufacturing process and also in operations of the final product semiconductor device.
These problems are particularly encountered in via locations of the device during manufacture. For example, the exposure energy and procedures to print vias must account for the greatest thicknesses of resist although resist thickness varies. This problem can result in overetch and underetch of portions on the same die because of lag problems that occur in that etch rates are slowed as the aspect ratio increases because of thicker resist. As used herein, aspect ratio of an opening is a ratio of the depth of the opening to the width of the opening.
Another problem includes xe2x80x9cside lobingxe2x80x9d when a phase-shifting mask is used. When radiation passes through a phase-shifting mask, a secondary peak in radiation occurs near the edge of the feature being printed in the resist. The resist requires higher levels of radiation to expose the resist at locations where the resist is thicker. However, if the radiation is too high, the secondary peak can exceed the level of energy needed to expose a pattern in the resist. Because these typically occur near the edge of a pattern, it is called xe2x80x9cside lobing.xe2x80x9d If the minimum exposure required for the thicker resist exceeds the maximum exposure before side lobing occurs, the process will not work. The problems described above are particularly apparent in trench first, via last (TFVL) manufacture procedures, which is a process for forming dual-inlaid openings for interconnects or the like, where trenches are formed before via openings. An example of the resist thickness variation is shown in FIG. 1. In FIG. 1, a portion of a semiconductor device workpiece 100 includes an insulating layer 102 where a narrow trench 103 and a wide trench 105 have previously been formed. The semiconductor device workpiece 100 is conventional in that it includes a semiconductor device substrate (not shown in full), such as a monocrystalline semiconductor wafer, a semiconductor-on-insulator substrate, or any other substrate suitable for use to form semiconductor devices. As those skilled in the art know and appreciate, the semiconductor device substrate can comprise various layers and configurations, including active, passive, insulative, conductive and other elements, as desired in the particular case.
A resist layer 104 is formed over the insulating layer 102 and within the trenches 103 and 105. Due to the shapes and locations of the trenches, viscosity of the resist layer 104 (when coated), and other fluid mechanical properties, the resist layer 104 is not planar at its uppermost surface and has different thicknesses in the wide trench 105 and the narrow trench 103. The resist layer 104 is patterned to correspond to via locations, which are locations where vias will be formed. With increased trench width, the resist thickness in the trench decreases. For example, the thickness A of the resist 104 in the narrow trench 103 is greater than the thickness B of the resist 104 in the wide trench 105.
Openings 106 and 108 are formed within the resist layer 104 to correspond to the via locations. Before forming openings 106 and 108, the resist layer 104 is significantly thicker where resist opening 106 (e.g. approximately 2.5 microns) will be formed compared to where the resist opening 108 (e.g., approximately 1.7 microns) will be formed. In some technologies, the energy of radiation required to expose the resist layer 104 in forming the opening 106 exceeds the maximum energy before side lobing will be seen when a phase-shift mask is used.
Even if the resist openings 106 and 108 can be formed, too much etch lag may occur. After forming the resist openings 106 and 108, the insulating layer 102 is etched to form via openings that typically connect to underlying conductors (not shown). The insulating layer 102 will etch more quickly under resist opening 108 because the aspect ratio of resist opening 108 is smaller than the aspect ratio of resist opening 106. The lower aspect ratio allows etchant and etch products to enter and leave the resist opening 108 more easily compared to resist opening 106. The result is that the insulating layer 102 needs a different amount of time to remove the insulating layer under resist openings 106 and 108. Problems can include not clearing all the insulating layer 102 under the resist opening 106 or overetching the underlying conductor (not shown) that lies below resist opening 108. Even if a relatively narrow opening is formed and the insulating layer 102 is cleared from it, the relatively wider openings may become too wide while clearing the insulating layer 102.